Using copper (Cu) for ultra large scale integrated (ULSI) metal interconnects has become the standard industry trend in semiconductor chip manufacturing since IBM announced copper dual-damascene process technology in September 1997. Void free fill of Cu into small aggressive feature sizes (e.g., currently <100 nanometers) with relatively high aspect ratios covered with continuous barrier and seed layers may be achieved with electroplating. The electroplating operation basically involves electrochemically depositing Cu onto the surface of a wafer. The whole surface of the wafer is covered with a continuous, thin deposited Cu seed layer that serves as a cathode electrode in the electroplating cell of the electroplating system.
On problem with prior electroplating operations is the accidentally processing of wafer without Cu seed coverage or poor seed coverage at the electrical contacts with a wafer. This can lead to Cu metal deposition occurring very near the electrical contact points of a plating system. As the deposits accumulate on the electrical contact points, pieces of the electroplating metal debris may fall into plating bath that can eventually cause serious plating defects on wafers that are subsequently processed. The corrective action requires the removal of the entire plating bath solution and the cleaning of all related processing equipment. Such corrective action may require significant system down time (the amount of time that the system is not available for use) and, thereby, have an impact on the plating system operational time. Therefore, the degree of plating coverage may be monitored by plating systems to ensure proper system operation.
One prior plating system by Novellus Systems Inc. (NVLS) has a clamshell configuration that insulates the wafer edge from the plating bath using an o-ring seal to prevent the electrolyte solution from getting inside the clamshell and, thereby, the electrical contact points, as illustrated in FIG. 1A. The electrical contact to the wafer is made with metal contact points placed near the edges of the wafer. A circuit resistance is measured between the contact points near the edge of the wafer. A significant resistance difference will exist between a metal edge covered wafer and a non-metal edge covered wafer surface. Such resistance differences are used by the NVLS system to detect whether a wafer has seed layer coverage on the edge. One problem with the NVLS system is poor edge uniformity on a processed wafer.
Another prior plating system by Applied Materials (AMAT) uses a laser edge detector, illustrated in FIG. 1B. The laser edge detector can distinguish a Cu seed covered edge from a non-covered edge by detecting a difference between a laser beam reflected from a Cu film edge and a non-Cu covered (e.g., barrier layer) edge. The AMAT plating system uses a thrust plate and contact ring that are exposed to the electroplating bath. One problem with the AMAT system is that no meaningful internal circuit can be available to allow wafer edge surface conductivity measurement because the contact ring is made of single piece of metal. Another problem with the AMAT system is that laser edge bevel removal (EBR) detection is extremely expensive and it is not reliable for detecting patterned wafers or wafers with only partial seed coverage. Yet another disadvantage is that the laser detection method may only be able to detect a Cu seed metal from a tantalum (Ta) or Ta alloy barrier layer surface based on the reflectivity. Its capability of distinguishing other metals from non-metallic surfaces remains unknown.